An integrated semiconductor circuit contains large numbers of electronic devices within a single substrate or "chip" with the electronic devices being selectively connected by electrical conductors to form functional circuits. Such semiconductor devices are formed in layers, quite often including an electrical conductor as a base or bottom most layer; and, additionally, different electronic devices are formed within different levels of layers with such devices being strategically placed over the available surface area or "geography" of the minute chip. This integrated circuit structure is accomplished by known processes.
To electrically connect together selected electronic devices located at different vertical positions in this three dimensional solid matrix characterizing the chip, into an electrical circuit, integrated circuits employ metal "plated through" holes. That is, minute sized passages, formed by known photolithographic etching technique, extend through the matrix intersecting electrically conductive material, the metal lines or layers located at different vertical levels; and a metal plating, an electrical conductor, is applied to the walls of the passages and, as desired, fills the entire passage. The metal plating provides an electrically conductive path between the conductive material at the two levels, much like the vertically extending plumbing pipes that extend through the different vertical levels of a high rise office building. The conductive path thus formed allows voltages and currents to pass between the circuits on one level or "floor" and another vertically spaced level. For additional background the reader may refer to the patent and technical literature on this subject.
Those skilled in the integrated circuit art have made increased efforts to effectively squeeze greater numbers of electronic devices within a given area of semiconductor substrate, increasing the "device density", by further reducing the size of individual semiconductor devices. As this device density increases, the channels and holes through the substrate layers necessarily are formed increasingly deep relative to the width of the hole; the holes have a "high aspect" ratio, greater than three to one. For example, typical holes may be one micron in diameter and three to four microns in depth for an aspect ratio of 3:1 to 4:1.
The high aspect ratio of the holes makes it difficult to attain quality metal plating: known metal sputtering processes and vapor deposition techniques appear to fail due to "shadowing" effects, wherein some metal atoms or ions traveling in random or uncontrolled directions strike the walls at an angle thus causing a metal growth along the top of the hole, causing "sidewall" growth, at the top of the hole, which is eventually closed. This leaves an internal void in the plating and results in poor electrical conductivity. Existing plasma techniques made known to applicant also failed to solve that problem.
Recognizing this technological difficulty, other workers in this subject have reported experiments in which a plasma containing a slightly ionized flux of aluminum atoms, approximately two per cent or less positively charged ions, are accelerated onto a target substrate, negatively biased by a very large voltage, to improve the filling of the high aspect ratio holes. As reported by S. N. Mei, S. N. Yang, & T. M. Lee & S. Roberts in a paper, "High Aspect Ratio via Filling with Al Using Partially Ionized Beam Deposition", presented at the AVS 34th National Symposium; Anaheim, CA. November 2-6, 1987, those experiments show that plasma plating of high aspect ratio holes is possible. It is noteworthy that the foregoing method and apparatus did not use a confining magnetic field, characteristic of the present invention, and used a low ion percentage plasma. The present invention provides a different and more effective solution to the technological difficulty encountered.
Likewise, the patent to Homma et. al. U.S. Pat. No. 4,717,462 granted January 5, 1988 for a "Sputtering Apparatus" describes a plasma plating apparatus in which a plasma is produced without a magnetic field generating apparatus as a solution to the problem of plating of high aspect ratio holes in substrate. That apparatus includes a metal screen, preferably of magnetic material, but which may also be non-magnetic, and in which either rf power or dc current power is applied to the substrate, the latter dc voltage being given in the example as of the same dc voltage level as the screen, electrical ground potential.
In its operation, Homma's screen appears to collimate the moving atoms in the plasma by preventing passage of atoms which are traveling toward the screen skew to the axis at too great an angle. Because of the random uncontrolled direction of movement of atoms and ions produced in the plasma generator if all such particles are allowed to travel to the substrate, the plating building up outside the holes would occur more quickly than inside - hence, the shadowing. By preventing those ions that do not follow generally an axial path from reaching the substrate, the build up of the metal in the holes and a more even metal coating on the surface of the substrate is possible, but at a reduced plating rate, since fewer atoms pass through the screen. In making the holes in the screen into tunnel like "high aspect ratio" passages the Homma patent notes that a more even coating is obtainable since more atoms cannot make it through the screen and the plating speed drops dramatically.
As becomes more apparent hereafter, the present invention does not seek to screen out ions or slow down the plating rate as a compromise to obtain a more even plating as appears to be the arrangement in the different apparatus of the Homma et. al. patent.
Another existing plasma apparatus inherently capable of applying or depositing metal plating on microelectronic circuit substrate is the Plasma Immersion Implantation Apparatus ("PII" apparatus) produced by TRW, Inc., Redondo Beach, CA, the assignee of the present invention that is described in U.S. Pat. No. 4,059,761 granted Nov. 22, 1977 to Dawson entitled "Separation of Isotopes By Time of Flight" (Dawson '761). Reference may be made to the Dawson '761 patent as additional background to the present invention. As shown in the patent, plasma apparatus is used to create positive ions of two different materials which can be separated or sorted and teaches techniques for creating a plasma containing positive ions.
More specifically, Dawson '761 discloses an apparatus for generating a plasma using a tungsten sputter plate, a source of potassium to be ionized and an RF source to expose the potassium to RF "heating" energy within an evacuated longitudally extending chamber with longitudal magnetic fields for confining the plasma away from the chamber walls, allowing positive ions to drift toward a metal collector at the distant end of the chamber as part of the described arrangement for separating isotopes. Although intended for a purpose different from plating of holes in microelectronic chip substrate, the present invention recognizes that the apparatus shown in the Dawson patent can employ metal ions to provide a metal coating on a substrate. A similar structure to Dawson is presented in U.S. Pat. No. 4,123,316 granted Oct. 31, 1978 to Tsuchimoto et. al. to which reference may be made for further background in magnetically confined plasma apparatus.
In applying the aforementioned Dawson apparatus to plating of microelectronic substrates it was found that one experienced the same unsatisfactory result as that encountered with vapor deposition plating techniques in plating high aspect ratio holes. It was discovered that the application of a voltage to the substrate and support had no energy adding effect on the ions of the plasma increasing the negative voltage on the substrate as was expected to attract positive metal ions to the substrate, to add longitudinal velocity to such ions, failed. Unexpectedly, the plasma appeared to change in lock step with the change in voltage.
Effectively the plasma remained latched to the voltage of the substrate. When the voltage applied to the substrate increased, the plasma voltage increased. Since there was no increase in the potential difference between the plasma and the substrate, energy could not be added to individual ions.
A dramatic change occurred upon the introduction of an electrically grounded screen to the plasma apparatus and a voltage was applied between the screen and the substrate support to create the structure described in this specification. The plasma voltage no longer locked to the voltage on the substrate support. Energy could be added to the metal ions. Successful hole plating occurred.
In retrospect it is surmised that the screen effectively "grounded" the plasma, decoupling the plasma from the substrate voltage and placing the plasma at electrical ground. When the voltage on the substrate was varied, the plasma voltage no longer changed with it; an electric field could thus be established through the portion of the plasma and permitted addition of energy increasing the longitudinal velocity of the plasma ions, while repelling the electrons in the plasma.
An object of the present invention therefor is to provide a new and more efficient apparatus and process for "through hole" plating of high aspect ratio holes in microelectronic integrated circuit substrate. A further object of the invention is to provide a plasma apparatus that is capable of plating minute hole walls with copper or aluminum metals with great speed. An additional object of the invention is to provide a microelectronic substrate hole plating apparatus that is adjustable or variable to ensure effective plating of different size holes and to ensure complete plating of any particular high aspect ratio passage in the substrate. A still further object of the invention is to achieve modifications to existing plasma plating apparatus to form new plasma plating apparatus capable of providing quality plating of high aspect ratio holes so as to retain the benefit of redeploying existing apparatus. And a still additional object of the invention is to improve integrated circuit fabrication processes.